| Telephone Ring Generator Mk 2 (UK/USA) |
Here is a
telephone ring cadence generator which will
generate both, what I will refer to as: UK and USA ringing
formats; please read further.
This is a switch selectable dual output "re-hashed" version of my previous (2007) design, and uses a field programmed EPROM for generating both versions of the ringing sequence.
We know that the ringing sequence's are such:
UK format: 400mS ring, 200mS silence, 400mS ring followed by 2 second silence
(3 second total - then cycle repeats) Ringing frequency of the bells reckoned to be about 25Hz
USA format 4 secs ring, 8 secs silent, 30Hz ringing frequency, then cycle repeats.
Referring now to the schematic:
AC mains is stepped down to about 10 v AC and fed to the familiar bridge rectifier, filter capacitor and 3 terminal voltage regulator. However a series diode is inserted between the + terminal of the bridge rectifier and the filter capacitor. Therefore at the anode end of this diode will be a pulsating 100Hz unidirectional sinusoid which is used as an accurate "clock" (Cathode end being filtered DC voltage)
This positive going sinusoid is fed to a 4093 Schmitt trigger, its action produces a fast rise (and fall) square wave output necessary to clock following logic IC's.
A clamping diode b/w the Schmitt input (pin 2) and the Vcc rail precludes the input from rising greater than one diode drop above Vcc, excess voltage being dropped across 1K resistor. It was found by experiment that a 22K "bleed" resistor was needed at the gate input to prevent "lock-up" due to some sort of "charge storage" effect.
This cleaned-up 100Hz "clock" signal is now fed to a 4013 D type flip-flop which divides the signal by 2 and also gives a 50 Hz equi' mark/space signal. This then feeds the 7490 where another divide by 2 gives; 25Hz (for ringing frequency) and further divide by 5 give 5Hz or a 200mS interval suitable for producing the correct ring cadence.
The 200mS interval pulse train feeds a 4040 ripple counter which will advance its count for each falling edge of the incoming clock.
The sequential outputs of the 4040 are connected to the address lines of a 2716 eprom which has been field programmed to provide a serial output bit-stream of 200mS interval used as a gating signal to enable on and off the 25Hz ringing signal.
For each 200mS clock pulse the output of the eprom moves to the next sequential address. The first 64 locations contain the necessary coding for two runs of the UK sequence and the next 64 memory addresses's contain coding for the 4 sec ring, 8 sec silence US sequence.
The cycle then repeats again from the starting address.
Either "bank" is enabled by the switch connected to the A6 address line (see schematic).
In fact, in my prototype I used the redundant 110/220v mains selector switch to do this job (although is obscured in photograph)
You will need some means of programming an eprom (ie. eprom "burner")
I have used the 2716 (2K x 8) device simply because I have plenty available and can program and erase them.
However the astute reader will realise that many other types would work, and in fact we are only using 128 address locations and one bit of the 8 bit wide data byte stored in the eprom (D0)
The eprom contents are shown in the table (below) it can be seen that the pink higlighted locations represent a "ring" and all others silence (read from top to bottom)
The eprom is a basically a look-up table of the ring sequence. Either format is switch selectable.
Gating is achieved in the 4093 NAND gate, its output then inverted directly feeds a VMOS FET gate which switches the unregulated 15v rail onto the transformer primary.
The VMOS FET is preferred over a bipolar transistor etc here because of their power handling capacity and very low "on" state resistance (milliohms) which allows most of the +15v DC rail be available to the transformer winding.
The VMOS FET should have some form of heat sink (even if small).
Fortunately these devices also have an internal reversed biased diode, b/w drain and source which protects them against failure from transient spikes (refer to manuf' data sheets).
The particular FET specified 2SK3296, I salvaged several from defunct P4 computer mother board (in power supply circuit). However suitable replacement types are easily available.
I have used a 5000 ohm to 4 ohm loud-speaker transformer (in reverse - so to speak) to step up the voltage to the level necessary the make the bell solenoid actuate the armature (1 : 35 ratio)
The specification for signal required to ring a telephone bell was a 25Hz , 75v swing (usually with a neg 50v DC bias).
The prototype I have fitted into a "recycled" metal box.
This box can be salvaged from discarded PC towers, being the switch mode power supply of the computer.
Simply remove the internals (circuit board, fan etc) and you have a 6" x 6" x 3" sized metal box with IEC entry connector and on/off mains switch etc - ready for re-use.
Blank off any larger holes with scrap metal material.
I have used wire-wrap sockets mounted on a hinged prototyping board to facilitate construction of the "electronics" hardware.
SCHEMATIC
Eprom contents:
In summing up, I have constructed and tested the above design and find it works well.
FRANK HUGHES VK6FH JAN' 2008.
This is a switch selectable dual output "re-hashed" version of my previous (2007) design, and uses a field programmed EPROM for generating both versions of the ringing sequence.
We know that the ringing sequence's are such:
UK format: 400mS ring, 200mS silence, 400mS ring followed by 2 second silence
(3 second total - then cycle repeats) Ringing frequency of the bells reckoned to be about 25Hz
USA format 4 secs ring, 8 secs silent, 30Hz ringing frequency, then cycle repeats.
Referring now to the schematic:
AC mains is stepped down to about 10 v AC and fed to the familiar bridge rectifier, filter capacitor and 3 terminal voltage regulator. However a series diode is inserted between the + terminal of the bridge rectifier and the filter capacitor. Therefore at the anode end of this diode will be a pulsating 100Hz unidirectional sinusoid which is used as an accurate "clock" (Cathode end being filtered DC voltage)
This positive going sinusoid is fed to a 4093 Schmitt trigger, its action produces a fast rise (and fall) square wave output necessary to clock following logic IC's.
A clamping diode b/w the Schmitt input (pin 2) and the Vcc rail precludes the input from rising greater than one diode drop above Vcc, excess voltage being dropped across 1K resistor. It was found by experiment that a 22K "bleed" resistor was needed at the gate input to prevent "lock-up" due to some sort of "charge storage" effect.
This cleaned-up 100Hz "clock" signal is now fed to a 4013 D type flip-flop which divides the signal by 2 and also gives a 50 Hz equi' mark/space signal. This then feeds the 7490 where another divide by 2 gives; 25Hz (for ringing frequency) and further divide by 5 give 5Hz or a 200mS interval suitable for producing the correct ring cadence.
The 200mS interval pulse train feeds a 4040 ripple counter which will advance its count for each falling edge of the incoming clock.
The sequential outputs of the 4040 are connected to the address lines of a 2716 eprom which has been field programmed to provide a serial output bit-stream of 200mS interval used as a gating signal to enable on and off the 25Hz ringing signal.
For each 200mS clock pulse the output of the eprom moves to the next sequential address. The first 64 locations contain the necessary coding for two runs of the UK sequence and the next 64 memory addresses's contain coding for the 4 sec ring, 8 sec silence US sequence.
The cycle then repeats again from the starting address.
Either "bank" is enabled by the switch connected to the A6 address line (see schematic).
In fact, in my prototype I used the redundant 110/220v mains selector switch to do this job (although is obscured in photograph)
You will need some means of programming an eprom (ie. eprom "burner")
I have used the 2716 (2K x 8) device simply because I have plenty available and can program and erase them.
However the astute reader will realise that many other types would work, and in fact we are only using 128 address locations and one bit of the 8 bit wide data byte stored in the eprom (D0)
The eprom contents are shown in the table (below) it can be seen that the pink higlighted locations represent a "ring" and all others silence (read from top to bottom)
The eprom is a basically a look-up table of the ring sequence. Either format is switch selectable.
Gating is achieved in the 4093 NAND gate, its output then inverted directly feeds a VMOS FET gate which switches the unregulated 15v rail onto the transformer primary.
The VMOS FET is preferred over a bipolar transistor etc here because of their power handling capacity and very low "on" state resistance (milliohms) which allows most of the +15v DC rail be available to the transformer winding.
The VMOS FET should have some form of heat sink (even if small).
Fortunately these devices also have an internal reversed biased diode, b/w drain and source which protects them against failure from transient spikes (refer to manuf' data sheets).
The particular FET specified 2SK3296, I salvaged several from defunct P4 computer mother board (in power supply circuit). However suitable replacement types are easily available.
I have used a 5000 ohm to 4 ohm loud-speaker transformer (in reverse - so to speak) to step up the voltage to the level necessary the make the bell solenoid actuate the armature (1 : 35 ratio)
The specification for signal required to ring a telephone bell was a 25Hz , 75v swing (usually with a neg 50v DC bias).
The prototype I have fitted into a "recycled" metal box.
This box can be salvaged from discarded PC towers, being the switch mode power supply of the computer.
Simply remove the internals (circuit board, fan etc) and you have a 6" x 6" x 3" sized metal box with IEC entry connector and on/off mains switch etc - ready for re-use.
Blank off any larger holes with scrap metal material.
I have used wire-wrap sockets mounted on a hinged prototyping board to facilitate construction of the "electronics" hardware.
SCHEMATIC
Eprom contents:
| Address | Data | Address | Data | Address | Data | Address | Data |
| 0000 | 01 | 0020 | 01 | 0040 | 01 | 0060 | 00 |
| 0001 | 01 | 0021 | 01 | 0041 | 01 | 0061 | 00 |
| 0002 | 00 | 0022 | 00 | 0042 | 01 | 0062 | 00 |
| 0003 | 01 | 0023 | 01 | 0043 | 01 | 0063 | 00 |
| 0004 | 01 | 0024 | 01 | 0044 | 01 | 0064 | 00 |
| 0005 | 00 | 0025 | 00 | 0045 | 01 | 0065 | 00 |
| 0006 | 00 | 0026 | 00 | 0046 | 01 | 0066 | 00 |
| 0007 | 00 | 0027 | 00 | 0047 | 01 | 0067 | 00 |
| 0008 | 00 | 0028 | 00 | 0048 | 01 | 0068 | 00 |
| 0009 | 00 | 0029 | 00 | 0049 | 01 | 0069 | 00 |
| 000a | 00 | 002a | 00 | 004a | 01 | 006a | 00 |
| 000b | 00 | 002b | 00 | 004b | 01 | 006b | 00 |
| 000c | 00 | 002c | 00 | 004c | 01 | 006c | 00 |
| 000d | 00 | 002d | 00 | 004d | 01 | 006d | 00 |
| 000e | 00 | 002e | 00 | 004e | 01 | 006e | 00 |
| 000f | 00 | 002f | 00 | 004f | 01 | 006f | 00 |
| 0010 | 01 | 0030 | 01 | 0050 | 01 | 0070 | 00 |
| 0011 | 01 | 0031 | 01 | 0051 | 01 | 0071 | 00 |
| 0012 | 00 | 0032 | 00 | 0052 | 01 | 0072 | 00 |
| 0013 | 01 | 0033 | 01 | 0053 | 01 | 0073 | 00 |
| 0014 | 01 | 0034 | 01 | 0054 | 00 | 0074 | 00 |
| 0015 | 00 | 0035 | 00 | 0055 | 00 | 0075 | 00 |
| 0016 | 00 | 0036 | 00 | 0056 | 00 | 0076 | 00 |
| 0017 | 00 | 0037 | 00 | 0057 | 00 | 0077 | 00 |
| 0018 | 00 | 0038 | 00 | 0058 | 00 | 0078 | 00 |
| 0019 | 00 | 0039 | 00 | 0059 | 00 | 0079 | 00 |
| 001a | 00 | 003a | 00 | 005a | 00 | 007a | 00 |
| 001b | 00 | 003b | 00 | 005b | 00 | 007b | 00 |
| 001c | 00 | 003c | 00 | 005c | 00 | 007c | 00 |
| 001d | 00 | 003d | 00 | 005d | 00 | 007d | 00 |
| 001e | 00 | 003e | 00 | 005e | 00 | 007e | 00 |
| 001f | 00 | 003f | 00 | 005f | 00 | 007f | 00 |
In summing up, I have constructed and tested the above design and find it works well.
FRANK HUGHES VK6FH JAN' 2008.